The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.
Computing architectures require memory to store data and instructions and generally benefit from having increased memory available. The types of memory vary from, for example, memory accessible within a central processing unit (CPU) to memory which is accessible, for example, through a backbone bus on a motherboard, to memory or storage within a persistent storage device, such as a hard disk drive or a high capacity solid state memory used for persistent storage.
Generally speaking, memory closer to the CPU may be accessed faster. Memory within a CPU may be referred to as cache, and may be accessible at different hierarchical levels, such as Level 1 cache (L1 cache) and Level 2 cache (L2 cache). System memory such as memory modules coupled with a motherboard may also be available.
CPU cache, such as L1 cache, is used by the central processing unit of a computer to reduce the average time to access memory. The L1 cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations. L2 cache may be larger, but slower to access. And system memory may be larger still, but slower to access then any CPU based cache. As long as most memory accesses are cached memory locations, the average latency of memory accesses will be closer to the cache latency than to the latency of main memory.
When the processor needs to read from or write to a location in main memory, it first checks whether a copy of that data is in one of its caches (e.g., L1, L2 caches, etc.) and when available, the processor immediately reads from or writes to the cache, providing a much faster result than reading from or writing to main memory of the system.
As the amount of space available within a CPU's cache increases, the likelihood of a cache hit increases, and thus, the CPU can operate at increased speeds as the CPU is not forced to wait for lengthy retrieval times from a system's main memory. However, as the amount of space increase, the increased size of addressable memory requires larger address sizes to handle the increase in uniquely addressable memory locations.
The present state of the art may therefore benefit from systems and methods for implementing and using a partial-address select-signal generator with address shift as described herein.